1. Field of the Invention
The present invention relates to semiconductor devices and a manufacturing method thereof and, more particularly, to a structure of a dynamic random access memory (DRAM) and a manufacturing method thereof.
2. Description of the Background Art
Recently, a demand for semiconductor memory devices among semiconductor devices has been rapidly increased, as information processing equipment such as computers has remarkably prevailed. Furthermore, semiconductor memory devices which have a large storage capacity and are capable of a high speed operation are required. Accordingly, technology development relating to high integration density, a high speed response and high reliability of a semiconductor device has been promoted.
Among semiconductor memory devices, a DRAM is known as a memory in which random input/output of stored information is performed. In general, the DRAM is comprised of a memory cell array portion which is a storage region for storing much information and a peripheral circuit portion necessary for external input/output. FIG. 38 is a block diagram showing a general DRAM structure. Referring to FIG. 38, a DRAM 120 includes a memory cell array 121 for storing a data signal of information, a row and column address buffer 122 for externally obtaining an address signal for selecting a memory cell which constitutes a unitary memory circuit, a row decoder 123 and a column decoder 124 for designating a memory cell by decoding the address signal, a sense refresh amplifier 125 amplifying and reading out a signal stored in a designated memory cell, a data in buffer 126 and a data out buffer 127 for data input/output, and a clock generator 128 for generating a clock signal.
Memory cell array 121 occupying a large area on a semiconductor chip has a plurality of memory cells for storing unitary stored information arranged in a matrix. That is, a memory cell is usually comprised of one MOS transistor and one capacitor connected thereto. This memory cell is widely known as a one-transistor-one-capacitor type memory cell. Since the structure of such a memory cell is simple, it is easy to increase integration density of a memory cell array and thus it is widely used for a DRAM with a large capacity.
Memory cells of DRAMs can be divided into several types according to the structures of their capacitors. In a stacked-type-capacitor, which is one of such types, a capacity of the capacitor can be increased by having the main portion of the capacitor extending onto a gate electrode and onto a field isolation film to increase an area where the electrodes of the capacitor face to each other. The stacked-type-capacitor has such a characteristic, so that the capacity of the capacitor can be secured even in a miniaturized semiconductor device with high integration density. Consequently, a stacked-type capacitor has been widely used, as integration density of semiconductor devices has been increased.
FIG. 39 is a sectional view of a DRAM having a conventional stacked-type capacitor. Referring to FIG. 39, a conventional DRAM includes a p type single crystalline silicon substrate 131; an isolation oxide film (a thick silicon oxide film) 132 for isolating elements formed on predetermined regions of a main surface of single crystalline silicon substrate 131; a pair of source/drain regions (n.sup.+ impurity implantation layer) 133a, 133b formed in a region surrounded with isolation oxide film 132 to have a channel region 145 interposed with a predetermined space therebetween; a gate electrode 136 formed on channel region 145 with a gate oxide film 135 interposed; an interlayer insulating film 137 formed to cover the whole surface and having contact holes 137a, 137b above n.sup.+ impurity implantation layers 133a, 133b; a capacitor lower electrode 138 of low-resistance polycrystalline silicon doped with phosphorus (P) connected to n.sup.+ impurity implantation layer 133b and formed to extend on interlayer insulating film 137; a capacitor upper electrode 140 of low-resistance polycrystalline silicon doped with phosphorus (P) formed on capacitor lower electrode 138 with a capacitor dielectric film 139 of Ta.sub.2 O.sub.5 or the like interposed; an n.sup.+ impurity diffusion layer 134 formed through thermal diffusion of impurities (P) of capacitor lower electrode 138; an interlayer insulating film 141 formed to cover the whole surface and having an opening above n.sup.+ impurity implantation layer 133a; a polycrystalline silicon film 142a electrically connected to n.sup.+ impurity implantation layer 133a and extending on interlayer insulating film 141; a silicide film 142b of WSi.sub.2 or the like formed on polycrystalline silicon film 142a; an interlayer insulating film 143 formed on silicide film 142b; and aluminum interconnections 144 formed on interlayer insulating film 143 with a predetermined space therebetween to correspond to gate electrodes 136.
A pair of n.sup.+ impurity implantation layers (source/drain regions) 133a, 133b and gate electrode 136 constitute a switching MOS transistor. A stacked-type capacitor is formed of capacitor lower electrode 138, capacitor dielectric film 139 and capacitor upper electrode 140 for storing charges corresponding to a data signal. A bit line 142 is formed of polycrystalline silicon film 142a and silicide film 142b.
FIGS. 40 through 47 are sectional views (the first step through the eighth step) showing a manufacturing process for a conventional DRAM shown in FIG. 39. Referring to FIGS. 39 through 47, a manufacturing process of a conventional DRAM will be described.
Referring to FIG. 40, isolation oxide film (thick silicon oxide film) 132 is formed for isolation in a predetermined region on the main surface of single crystalline silicon substrate 131 using a LOCOS (Local Oxidation of Silicon) method.
Referring to FIG. 41, a gate oxide film layer (not shown) is formed on the whole surface using a thermal oxidation method, and a low-resistance polycrystalline silicon layer (not shown) doped with impurities (P) is deposited on the gate oxide film layer using a CVD (Chemical Vapor Deposition) method. Patterning is then carried out using lithography and dry etching to form gate oxide film 135 and gate electrode 136.
Referring to FIG. 42, a pair of n.sup.+ impurity implantation layers (source/drain regions) 133a, 133b are formed in a self aligned manner by ion implantation of arsenic (As) on conditions of 50 KeV, 4.times.10.sup.15 /cm.sup.2 using gate electrode 136 as a mask, as shown in FIG. 42. Thereafter, n.sup.+ impurity implantation layers 133a, 133b are electrically activated through a heat treatment.
Referring to FIG. 43, interlayer insulating film 137 is formed on the whole surface using the CVD method.
Referring to FIG. 44, a contact hole 137a is formed in a region on a first impurity region 133b of interlayer insulating film 137 using lithography and dry etching.
Referring to FIG. 45, after the low-resistance polycrystalline silicon layer (not shown) doped with phosphorus (P) is formed on the entire surface using the CVD method, capacitor lower electrode 138 is formed by patterning, using lithography and dry etching. The step of forming capacitor lower electrode 138 by the CVD method is carried out at temperature of about 700.degree. C., so that impurities (phosphorus) in capacitor lower electrode 138 are thermally diffused to single crystalline silicon substrate 131. Thus, n.sup.+ impurity diffusion layer 134 is formed. As a result, capacitor lower electrode 138 and n.sup.+ impurity implantation layer 133b are electrically connected.
Referring to FIG. 46, capacitor dielectric film 139 is formed on capacitor lower electrode 138. Capacitor dielectric film 139 is formed of a single layered film such as a thermal oxide film, a multi-layered film having a structure of, for example, a silicon oxide film/a silicon nitride film/a silicon oxide film, or Ta.sub.2 O.sub.5. After a low-resistance polycrystalline silicon film layer (not shown) doped with phosphorus (P) is formed using the CVD method, capacitor upper electrode 140 is formed by patterning, using lithography and dry etching. Interlayer insulating film 141 is formed on the whole surface using the CVD method. For flattening of the upper surface of interlayer insulating film 141, a heat treatment is carried out at temperature of about 850.degree. C. by a reflow method.
Referring to FIG. 47, contact holes 137a and 141a are formed in a region located on n.sup.+ impurity implantation layer 133a in interlayer insulating films 137 and 141 using lithography and dry etching, so that a part of n.sup.+ impurity implantation layer 133a is exposed. Polycrystalline silicon film 142a doped with impurities is formed to electrically connect with the exposed n.sup.+ impurity implantation layer 133a and extend on interlayer insulating film 141. A silicide film 142b of WSi.sub.2 or the like is formed using a sputtering method on polycrystalline silicon film 142a. Interlayer insulating film 143 is formed on the whole surface using the CVD method. For flattening of the surface of interlayer insulating film 143, a heat treatment at temperatures of about 850.degree. C. is carried out by a reflow method.
Finally, as shown in FIG. 39, aluminum interconnections 144 are formed with predetermined spaces therebetween.
As described above, a conventional DRAM has been formed.
In a memory cell forming a conventional DRAM, as described above, impurities (phosphorus) in capacitor lower electrode 138 is thermally diffused toward silicon single crystalline substrate 131, so that n.sup.+ impurity diffusion layer 134 is formed to electrically connect n.sup.+ impurity implantation layer 133b and capacitor lower electrode 138. That is, through thermal diffusion by heat at about 700.degree. C. in forming capacitor lower electrode 138, n.sup.+ impurity diffusion layer 134 is formed.
However, as shown in FIG. 46, after interlayer insulating film 141 is formed, heat at about 850.degree. C. is applied in the reflow method for flattening of the surface. Consequently, impurities (phosphorus) in capacitor lower electrode 138 are further diffused towards single crystalline silicon substrate 131. As a result, the diffusion region of n.sup.+ impurity diffusion layer 134 is further enlarged, resulting in a disadvantage that an end portion B of n.sup.+ impurity diffusion layer 134 extends from an end portion A of n.sup.+ impurity implantation layer 133b on the side of gate electrode 136. Furthermore, as shown in FIG. 47, interlayer insulating film 143 is also subjected to a heat treatment at about 850.degree. C. in the reflow method for flattening so that impurities (phosphorus) in capacitor lower electrode 138 are further diffused towards single crystalline silicon substrate 131 and thus n.sup.+ impurity diffusion layer 134 is further diffused to the side of the gate electrode.
When a region of n.sup.+ impurity diffusion layer 134 on the side of gate electrode 136 protrudes from n.sup.+ impurity implantation layer 133b and extends under gate electrode 136, the following problems may arise.
An effective gate length L.sub.0 of gate electrode 136 is shortened by the extended area of n.sup.+ impurity diffusion layer 134 from n.sup.+ impurity implantation layer 133b. That is, the effective gate length becomes L.sub.l. As a result, a so-called short channel effect is produced in which a threshold voltage of a switching MOS transistor is decreased. When the channel length is short, a depletion layer in the vicinity of n.sup.+ impurity implantation layer 133a which is to be a drain region in data writing extends to n.sup.+ impurity diffusion layer 134 which is to be a source region, and therefore, a problem may arise that a so-called punch through phenomenon tends to occur in which current can not be controlled by a gate voltage. In addition, n.sup.+ impurity diffusion layer 134 is not formed in a self aligned manner as n.sup.+ impurity implantation layer 133b, so that the extended area of n.sup.+ impurity diffusion layer 134 from n.sup.+ impurity implantation layer 133b varies depending on variation of alignment of gate electrode 136 and capacitor lower electrode 138 in patterning. As a result, a problem arises that transistor characteristics such as a threshold voltage vary.
FIG. 48 is a sectional view of structure of a DRAM having another conventional stacked-type capacitor. With reference to FIG. 48, this conventional DRAM includes a P type single crystalline silicon substrate 241 having a trench 241a formed in a predetermined region on a main surface thereof, an isolation oxide film 242 for elementary isolation which is formed on the main surface of single crystalline silicon substrate 241 and is adjacent to trench 241a, an n.sup.+ impurity implantation layer 243b having its end portion formed to be in contact with a sidewall of trench 241a, an n.sup.+ impurity implantation layer 243a formed to interpose a channel region 257 between n.sup.+ impurity implantation layers 243a and 243b with a predetermined space from each other, an n.sup.+ impurity implantation layer 244 formed along a surface of trench 241a, a gate electrode 247 formed on channel region 257 with a gate oxide film 246 interposed therebetween, an interlayer insulating film 248 having contact holes 248a and 248b, respectively, above n.sup.+ impurity implantation layer 243a and a recessed portion 241a, a capacitor lower electrode 250 made of a lower resistance polycrystalline silicon film including a large amount of impurities (phosphorus (P) of 4-8.times.10.sup.20 /cm.sup.3) formed to extend on a surface of interlayer insulating film 248, and formed on n.sup.+ impurity implantation layer 244 located at a bottom and a sidewall of recessed portion 241a, a capacitor dielectric film 251 formed on capacitor lower electrode 250, a capacitor upper electrode 252 formed on capacitor dielectric film 251, an n.sup.+ impurity diffusion layer 245 formed by thermal diffusion of impurities in capacitor lower electrode 250, an interlayer insulating film 253 formed to cover the whole surface and having a contact hole 253a above n.sup.+ impurity implantation layer 243a, a polycrystalline silicon film 254a electrically connected with n.sup.+ impurity implantation layer 243a in contact holes 248a, 253a, and formed along the surface of interlayer insulating film 253, a silicide film 254b formed on polycrystalline silicon film 254a, an interlayer insulating film 255 formed on silicide film 254b, and aluminum interconnections 256 formed with predetermined spaces from each other on interlayer insulating film 255. The conventional DRAM of another type having such a structure also has similar problems to those of the conventional DRAM shown in FIG. 39. That is, for flattening of the surfaces of interlayer insulating films 253 and 255, a heat treatment at about 850.degree. C. is carried out by a reflow method. This heat treatment causes impurities (phosphorus) within capacitor lower electrode 250 to thermally diffuse toward single crystalline silicon substrate 241. As a result, a diffusion area of n.sup.+ impurity diffusion layer 245 further extends, resulting in a disadvantage that an end portion B of n.sup.+ impurity diffusion layer 245 extends from an end portion A of n.sup.+ impurity implantation layer 243b on the side of gate electrode 247 to its lower part. This results in occurrence of a short channel effect and liability of a punch through phenomenon.